The present invention relates in general to integrated circuit design and, more particularly, to estimating power consumption of an architectural-level integrated circuit design.
Modern integrated circuits are being designed using high levels of design abstraction which are manually or automatically translated to lower levels of design detail. For example, a designer typically describes a circuit behaviorally using Hardware Description Language (HDL) or a similar behavioral modeling language. A series of design tasks are executed to convert the behavioral description to register transfer level (RTL), gate, transistor, layout, and mask level descriptions of the circuit. The behavioral description typically is the highest level of abstraction and has the least detail, while the mask description is typically the lowest level of abstraction and has the most detail. Higher levels of abstraction can be simulated more efficiently than lower levels, in part because less data is involved.
The behavioral description consists almost entirely of behavioral information with little or no structure. As the design is translated to successively lower levels of abstraction, the amount of structural information typically increases and the amount of behavioral information typically decreases. For example, a typical RTL description of a circuit includes circuit blocks which are defined to have a large degree of functionality but which also include such structural features as input and output ports or bus lines.
The power consumption of an integrated circuit largely depends on the structure of the circuit. Accuracy in predicting power consumption improves as the amount of structural information increases. The best accuracy is obtained when power consumption is estimated at a low abstraction level, such as the logic gate or transistor level. However, design efficiency improves when power can be estimated with reasonable accuracy at the behavioral level because designers are able to explore and analyze alternative designs more quickly at an early design stage.
Prior art methods delay power estimation until the design is transformed into a lower-level description, such as a gate-level or transistor-level description. However, a major redeployment of design and computing resources is needed if significant design modifications are made at a late design stage.
Hence, a need exists for an accurate, high-level power estimation system that allows a designer to explore and analyze alternative implementations of a design at an early stage in the design process.